This application claims the priority of Korean Patent Application No. 2003-12809, filed on Feb. 28, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to an interfacing circuit, which is located between external input pins and a memory core of a semiconductor memory device, for reducing current consumption of the semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device that receives a packet-type command from an external controller to perform operations in accordance with the command decodes the packet-type command and performs operations corresponding to the decoded result.
In the case where a command is input from the external controller, for example, in the case where a plurality of commands are input simultaneously, a general semiconductor memory device decodes the plurality of commands unconditionally and performs the operations corresponding to the decoded result.
FIG. 1A is a timing chart illustrating row activation packets among the packet commands used in the semiconductor memory device.
FIG. 1B is a timing chart illustrating row command packets among the packet commands used in the semiconductor memory device.
Referring to FIGS. 1A and 1B, in this example, four cycles of a clock signal CTM/CFM constitute one packet command. That is, commands input during the four cycles are collected to form one command for performing a single operation.
FIG. 1A shows a row activation packet containing information related to a number of a device to be accessed and a bank address as well as a row address to be accessed. DR represents the number of the device to be accessed, BR represents the bank address to be accessed, and R represents the row address to be accessed.
FIG. 1B shows a row command packet containing information related to a command, such as an activation command, or a precharge command, and the like.
FIG. 2 is an example of a command list of the row command packets.
The external memory controller of the semiconductor memory device sends the command defined in the command list of FIG. 2 to the semiconductor memory device, and the semiconductor memory device performs the operations corresponding to the received command.
FIG. 3 is a block diagram of a conventional interfacing circuit that decodes packet commands and controls a semiconductor memory device.
A command decoder 310 decodes a packet command input from the memory controller (not shown) and outputs a corresponding command. The input packet command is one among the commands defined in the command list of FIG. 2.
For example, if a packet command for sensing the memory cells of the memory core, such as a refresh command, is input, a corresponding master signal REFA is generated at a high level. Then, a control signal REFA_CTRL at a high level for sensing the memory cells is generated from a flip-flop 340 following one clock of the clock signal CLK. In this case, the remaining master signals PRER and REFP stay in a non-activated state.
However, in the case where a plurality of commands among the commands defined in the command list of FIG. 2 are generated simultaneously with the refresh command and input to the semiconductor memory device, the semiconductor memory device attempts to decode the plurality of commands and perform the corresponding operations. As a result, the semiconductor memory device operates incorrectly and consumes a large amount of electrical current by attempting to simultaneously process the commands and the refresh operation, thereby adversely affecting the performance of the entire memory system and the semiconductor memory device.